`timescale 1ns/1ps

`include ".\code\source\P0\id_fsm.v"


module test_id_fsm;

// Input
reg [7: 0] char;
reg clk;

// Output
wire out;

id_fsm u_id_fsm(
           .char (char ),
           .clk (clk ),
           .out (out ));

parameter Clock = 10;
parameter Clock_Half = 5;
integer loop;

initial begin
    clk <= 0;
    char <= 65;
    #Clock;
    char <= 66;
    #Clock;
    char <= 67;
    #Clock;
    char <= 48;
    #Clock;
    char <= 49;
    #Clock;
    char <= 1;
    #Clock;
    char <= 65;
    #Clock;
    char <= 97;
    #Clock;
    char <= 48;
    #Clock;
    char <= 122;
    #Clock;
    char <= 48;
end

initial begin
    for (loop = 0;loop < 500;loop = loop + 1) begin
        #Clock_Half;
        clk = ~clk;
    end
end

initial begin
    $dumpfile("./release/test_id_fsm.vcd");
    $dumpvars(0, test_id_fsm);
end

endmodule
